Digital IC Design Team Leader

Job Title            Digital IC Design Team Leader

Contract type   Permanent

Starting Date    Immediately

Location            Paris - FRANCE

Offer date         01/09/2020

Offer Ref.          scx_dig_lead_2020_01

Job function    SCALINX’s design team is seeking a dynamic and experienced leader who will manage a digital IC design team of around 10 people from concept to GDSII.

The candidate will work in close collaboration with the mixed-signal design team to deliver a state-of-the-art ASIC in deep submicron CMOS technology.

Work description

  • Lead and support a digital IC design team of 10 people from RTL to GDSII
  • Participate, in close collaboration with the Analog/Mixed-Signal architect and project technical leader, to the definition of the ASIC architecture and verification methodology.
  • Participate to discussion with customer on product architecture and specification definition.
  • Drive the architecture definition of the digital part
  • Drive, in close collaboration with the digital front-end and back-end team, the specifications of the ASIC digital sub-blocks to get the best area/power trade-off
  • Work in close collaboration with the back-end team to define the floorplan strategy to meet the stringent timing requirements
  • Define and drive the design and verification methodology at chip level and sub-blocks level
  • Define the test strategy and drive its implementation
  • Interact with EDA providers to give the best support to the design team and improve the use of tools
  • Participate to the evaluation of the fabricated ASIC in our measurement lab
  • Work in team to successfully design a state-of-the art ASIC
  • Animate design reviews
  • Write documentation in accordance with company QA policy

Qualification and Experience

  • You have a MSc or PhD in Electrical Engineering or equivalent and 10+ years of hands-on experience in chip-level and circuit-level architecture definition, RTL design and verification
  • You have a solid background in digital electronic and signal processing
  • You have a very good vision of the entire digital ASIC design flow from RTL to GDSII
  • You have a strong experience in digital ASIC project and team management
  • You have an experience in the design of high-speed digital signal processing blocks with multi-power and multi-clock domain constraints
  • You have solid knowledge of a digital hardware description languages (VHDL or Verilog), System Verilog and scripting languages (TCL, Perl, Python)
  • You are creative and proactive
  • You demonstrate good analytical and problem-solving skills
  • A previous experience in design and verification of digital functions for Mixed-Signal ASICs such as A/D Converters, D/A Converters, and/or RF transceivers is a plus
  • A previous experience with Cadence or Synopsys RTL design flow is a plus
  • You are a team player with a critical attitude and sense of initiative
  • You communicate fluently in English (oral and written)

How to apply

If you have a passion for IC design and the ambition to create outstanding products, it will be a great pleasure to receive your resume at


SCALINX is a fabless semiconductor company headquartered in Paris with a solid experience in design of Signal Conversion ASICs for Test & Measurement, Defense & Aerospace and Communications markets.
We help our customers to reduce the cost and shorten the development time with our Smart Conversion Platform based on proprietary SCCORETM technology.

The SCCORETM technology enables data conversion solutions where signal filtering and resolution trade-offs are carried out in programmable digital circuitry. The flexibility and programmability ingredients of the SCCORETM technology combined with our Signal Conversion IP blocks are key for complex ASIC projects. The tailored ASIC developments are supported by our three design centers, Paris, Caen and Sophia-Antipolis.           

If you have a passion for IC design and the ambition to create something different, it will be a great pleasure to receive your resume at