Digital verification engineer Team Leader (W/M)

Job Title Digital verification engineer Team Leader  (W/M)
Contract type Permanent
Starting Date Immediately
Location Paris, Caen - FRANCE
Offer date 23/11/2022
Offer Ref. scx_dig_verif_lead_2022_01


Job function  SCALINX’s design team is seeking a dynamic and highly motivated Digital IC verification engineer Team Leader to manage a digital verification team. In this role, the candidate will drive digital verification work-packages to deliver state-of-the-art Integrated Circuit (IC) in advanced CMOS technology in closed cooperation with mixed-signal and digital IC design engineers.

Work description 

  • Animate and work with the team to successfully design a state-of-the art ASSP
  • Manage verification team on a everyday basis and annual evaluation
  • Be a technical reference for your domain of expertise
  • Train and share knowledge with the team members
  • Drive verification methodologies
  • Interact with EDA providers to give the best support to the design team and improve the use of tools
  • Elaborate detailed verification plan corresponding to the circuit specifications
  • Write block and top-level self-checking test benches
  • Implement regression tests on RTL and gate-level netlists
  • Support the Analog design team in mixed-signal simulations
  • Participate to the evaluation of the fabricated ASSP in our measurement lab
  • Write documentation in accordance with company QA policy

Qualification and Experience 

  • You have a MSc or PhD in Electrical Engineering or equivalent and 10+ years of hands-on experience in digital IC verification
  • You have a previous experience in team management
  • You have a solid background in digital electronic
  • You have solid knowledge of a digital hardware description languages (VHDL or Verilog) and scripting languages (TCL, Perl, Python)
  • You have solid knowledge of System Verilog
  • Experience of UVM methodology is a plus
  • Experience in formal verification is a plus
  • Experience in gate-level simulation is a plus
  • You demonstrate good analytical and problem-solving skills
  • A previous experience in verification of digital functions for Mixed-Signal SoC
  • A previous experience with Cadence or Synopsys RTL design flow is a plus
  • A previous experience with FPGA is a plus
  • You are a team player with a critical attitude and sense of initiative
  • You have a strategic approach
  • You communicate fluently in English (oral and written)

How to apply 

If you are motivated to participate to the creation of outstanding products in a dynamic environment, it will be a great pleasure to receive your resume at

SCALINX is committed to diversity & equity, we aim to improve disability inclusion within our workforce.