Senior DFT engineer (W/M)

Job Title Senior DFT engineer (W/M)
Contract type Permanent
Starting Date Immediately
Location Paris/Caen/Grenoble - FRANCE
Offer date 22/10/2022
Offer Ref. scx_ams_tech_lead_2022_01

 

Job function SCALINX’s design team is seeking a dynamic and highly motivated senior DFT engineer who will participate to the design of a state-of-the-art CMOS Transceiver ASIC for the Communications market. The candidate will drive and execute the definition and implementation of DFT in the chip in closed relationship with the physical implementation as well industrialization teams.

Work description 

  • Responsible for the DFT architecture and drive and execute the DFT implementation of a complex SOC in advanced CMOS process (sub 20nm technologies)
  • Responsible for the development of a DFT flow (HW DFT insertion, test vectors generation, validation)
  • Responsible for the analysis of digital DFT metrics of proposed DFT solutions in view of the DFT requirements (test time, yield and default rate).
  • Advise digital design engineers on designing testable functional modules
  • Work closely with the RTL design team, physical implementation team to ensure a seamless integration of DFT features without impact the SOC performances.
  • Work closely with the industrialization team to define the optimum DFT solution (test time, yied) and provide the ATPG test vectors for production testing.
  • Work in team to successfully design a state-of-the art SOC
  • Participate to design reviews
  • Write documentation in accordance with company QA policy

 

Qualification and Experience 

  • You have a MSc or PhD in Electrical Engineering or equivalent and 10+ years of hands-on experience in DFT implementation in complex digital and/or SOC circuits.
  • You have good knowledge in RTL design
  • You have knowledge of scripting languages (TCL, Perl, Python)
  • You have hands-on experience with ATPG, BIST, ECC and Redundancy
  • You have hands-on experience with ASIC test methods (Iddq, delay test, very low voltage test) and on silicium physical and electrical defects (stuck-at, brieging…)
  • You have a strong knowledge of JTAG (IEEE1149.1, IEEE1149.3), logic tests (boundary scan, ATPG) and memory tests.
  • A previous experience with Cadence DFT design flow is a strong plus (Genus, Modus)
  • An experience with large designs (>1M gates) with advanced CMOS technologies (22nm and below) is a plus
  • You demonstrate good analytical and problem-solving skills
  • You are a team player with a critical attitude and sense of initiative
  • You communicate fluently in English (oral and written)

How to apply 

If you have a passion for IC design and the ambition to create outstanding products, it will be a great pleasure to receive your resume at jobs@scalinx.com

 
SCALINX is committed to diversity & equity, we aim to improve disability inclusion within our workforce.