Job Title Senior RF DAC Architect
Contract type Permanent contract
Starting Date Immediately
Location Paris, Caen - France
Job function SCALINX is seeking a Senior RF DAC architect who will define and drive the design of high-speed high-performance wideband Digital to Analog Converter (DAC) functions to be integrated in our next RF SoC product dedicated to the 5G Communication
market. In close collaboration with the AMS, Digital and layout engineers and the silicon
evaluation team, the candidate will be particularly involved in the architecture definition
of the DAC including mixed-signal and/or fully digital calibration techniques, the
definition of the sub-blocks specification, the floorplan strategy and the test strategy.
The Mixed-Signal IC architect will report to SCALINX CTO.
- In close relation with the RF SoC architect, translate the customer requirement into a DAC specification (resolution, Noise Spectral Density, harmonic Distortion, SFDR).
- Benchmark RF DAC state of the art
- Define the DAC architecture and the calibration techniques to meet the dynamic
specification with the lowest power consumption.
- Work closely with the RF SoC architect and other designers to specify interface
- Create high level ADC behavioral model
- Work closely with the digital system architect and designers to define the interface
between the DAC cells and the digital processing functions including DPD.
- Define the specification of the AMS sub-blocks and digital sub-blocks of the DAC
including calibration circuits.
- Discuss with the layout team floor planning and an isolation strategy to protect the sensitive analog/RF portions of the DAC against the noisy aggressors.
- Contribute to the definition of a simulation strategy to validate the DAC performances and calibration techniques with the rest of the DAC sub-blocks.
- In close collaboration with the silicon evaluation team, contribute to the definition of integrated test points/pattern, the evaluation plan and production test strategy.
- Participate to design reviews.
- Participate to characterization.
- Write documentation.
Qualification and Experience
- MSc or PhD in Electrical Engineering or equivalent with at least 10 years of
experience in designing and evaluating high-speed high-performance DAC functions.
- Experience in specifying high-speed high resolution Digital to Analog Converters
architecture in advanced CMOS process.
- Experience in designing mixed-signal functions such as ADC and/or DAC is
- Deep understanding of error mechanisms that affect the linearity and noise
performance of DAC.
- Experience in definition and implementation of calibration techniques to compensate for the static and dynamic errors in high speed high resolution DAC.
- Good understanding of digital and analog signal processing PRO/CONS to leverage the best of the two worlds.
- Very good vision of the entire analog & mixed-signal IC design flow
- Strong leadership and communication skills to work with AMS, Digital and layout
teams as well as the silicon evaluation team.
- Experience with product development cycles from concept to production
- Team player with a critical attitude and sense of initiative
- Fluent communication in English (oral and written) is a must
How to apply
- If you have a passion for IC design and the ambition to create something different, it will be a great pleasure to receive your resume at email@example.com
SCALINX is a fabless semiconductor company specialized in the design and supply of highly integrated semiconductor solutions for Communications, Aerospace & Defense and Industrial markets. We offer turnkey semiconductor devices, evaluation kits, and integration services, to help equipment manufacturers (OEM) solving their tightest signal conversion challenges. Our semiconductor devices integrate RF/Analog, Mixed-Signal and Digital HW/SW functions on the
same die or in the same package, enabling state-of-the-art RF Transceiver IC, Analog Front-End IC,
and RF SoC.
Our chips are built on a proprietary and protected Smart Conversion CORE (SCCORETM) technology, allowing power-efficient analog and digital processing of wideband signals. The chips development is supported by our tree design centers located in Paris, Caen and Grenoble.