Technical Leader Back-End (W/M)

Job function SCALINX’s Design Team is a looking for a dynamic and experienced Back-End Technical Leader who will contribute to define, implement and follow-up on the Back-End technical aspects. The candidate will also animate and develop their technical expertise. The technical leader will support the Chief Product Officer team in the definition of new products and in interface activities with customers.

Work description 

• Be responsible for the methodology, the design cycle of all physical partitions and the top level of all circuits, the maintenance and evolution of the development flow, and technological monitoring
• Ensure permanent and effective support on all aspects of Hand-Off between the Back-End Digital team and FE design/Layout Analog.
• Ensure the technical objectives and quality of the product as well as the development process. Ensure that the work produced is properly documented.
• Lead, organize, and participate in design reviews
• Support the development team based on the analysis of customer feedback
• Develop and own physical design implementation of multi-hierarchy low-power designs, including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes
• Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
• Deliver physical design of an end-to-end IP or integration of ASIC/SoC design.

Qualification and Experience 

• Bachelor’s degree in Electrical Engineering or equivalent similar experience
• More than 10 years’ of experience in physical design
• Understanding of RTL2GDSII flow and design tape-outs in FDSOI and FinFet process technologies.
• Experience with low power implementation, power gating, multiple voltage rails, UPF/CPF knowledge
• Experience working with EDA tools like DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus, or Calibre
• Experience running physical-aware logic synthesis and achieving optimal synthesis QoR on low-power designs
• Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions
• Experience in Block-level and Full-chip floor-planning (ideally with IOs bumps) and power grid planning
• Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques
• Experience with Python, TCL, Perl scripting
• Bilingual French & English
• Ability to analyze and solve problems.

How to apply 

If you have a passion for IC design and the ambition to create outstanding products, it will be a great pleasure to receive your resume at [email protected]

SCALINX is committed to diversity & equity, we aim to improve disability inclusion within our workforce.